As more input/output (I/O) requirements increase, traditional wire-bound packages will not effectively support thousands of I/Os. Flip-chip assembly technology is widely used to replace wire bonding technology because it not only reduces chip area, but also supports much more I/O. Flip-chips also greatly reduce the inductance to support high-speed signals and have better thermal conductivity. Flip-chip ball grid arrays (FCBGA) are also increasingly used for high I/O count chips.
Figure 1: Flip-chip cross-section: The signal lines pass through three faces, including the rewiring layer.
The Rewiring Layer (RDL) is the interface between the chip and the package in the flip chip assembly (Figure 1). The rewiring layer is an additional metal layer consisting of core metal top traces that are used to bond the die's I/O pads outward to other locations such as bump pads. The bumps are usually arranged in a grid pattern, and each bump is cast with two pads (one at the top and one at the bottom) which are connected to the rewiring layer and the package substrate, respectively. Therefore, the rewiring layer is used as a layer connecting the I/O pads and the bump pads.
Figure 2: Free allocation (FA) and pre-allocation (PA) are two methods of pad assignment. Peripheral I/O (PI/O) and Area I/O (AI/O) are two flip-chip structures.
Flip chip structure and pad assignment
Previous studies have identified two flip-chip structures and two pad assignment methods, as shown in Figure 2. Free allocation (FA) and pre-allocation (PA) are two methods of pad assignment, while peripheral I/O (PI/O) and area I/O (AI/O) are two flip-chip structures.
The difference between the two pad assignment methods is whether the mapping between bump pads and I/O pads is defined as an input. The problem with free allocation is that each I/O pad can be freely distributed to any bump pad, so the distribution and wiring need to be considered together. For pre-allocation, each I/O pad must be connected to a specified bump pad, so complex cross-connect problems need to be addressed. The solution to the pre-allocation problem is more difficult than automatic allocation, but it is more convenient for the designer.
The two flip chip structures represent different I/O layout patterns, respectively. The challenge of AI/O and PI/O is to place the I/O in the central area and place the I/O on the periphery of the die. Currently PI/O is more popular because it is simpler and has lower design costs, although AI/O can theoretically provide better performance.
Figure 3 shows a PI/O example. A green circle around the periphery represents the I/O pad. The red and yellow circles represent the power and ground bumps, while the blue circles represent the signal bumps. Those power/ground bumps located in the center of the die are classified into mesh types, and signal bumps are classified into raster types.
Figure 3: Top view of the rewiring layer showing the bump pads of the grid pattern and the peripheral I/O pads.
All of the above work is concentrated on single layer wiring. They limit the wiring to a single metal layer, and each network must be routed at this layer. The general goal is to reduce the length of the trace as much as possible. The optimization algorithm needs to be completed with a throughput rate of 100%. This approach has proven to be a good solution to the cabling problem for each rewiring layer, provided there is a single layer solution.
Practical rewiring layer wiring scheme
Rewiring layer routing and bump assignment are additional implementation tasks that help the design transition from wire bonding to flip chip. Bump assignment means assigning each bump to a specified I/O pad. Since the I/O pads are located on the periphery of the die for most designs, the flying leads and signal traces look like a mesh pattern from the center of the chip to the perimeter of the chip.
Figure 3 shows an example of a true scale design using a two-layer rewiring layer. Metal layer 10 (M10) and metal layer 9 (M9) complete all signal network wiring and implement power/ground (PG) grid and power wiring, respectively. There are usually a large number of signal networks that require wiring. The footprint of the bump pad is relatively large, and is often considered to be an obstacle to the wiring during the wiring phase.
Figure 4: Cabling solution for a crowded rewiring layer.
Figure 4(a) shows an example of a crowded rewiring layer in which the six networks netA, netB...netF are shown as flying lines. This design is so congested that it is impossible to achieve a 100% throughput rate on a single layer (such as M10). One solution is to increase the area of ​​the rewiring layer (such as M10). This is equivalent to increasing the die size as shown in Figure 4(b). Another solution is to add another layer of rewiring (such as M11), as shown in Figure 4(c). Although practical from the engineering point of view, both solutions are unacceptable from a cost perspective.
Alternative framework
A more practical option is the concept known as pseudo-single-layer routing, which takes up a small area on an existing metal layer (such as M9). This approach is operational and cost-effective if the occupied area is used for non-performance critical functions.
In Figure 4(d), some areas of M9 (pink areas) are used to complete the routing. Here we assume that the area between the boundary line (the gray line of the dot) and the die boundary is used for auxiliary wiring. The pseudo single layer wiring method avoids cost issues and reduces the difficulty of crowded wiring. Although the foregoing work has focused on single layer wiring, the pseudo single layer wiring uses two layers of wiring in a small area.
This method is suitable for rewiring layers because M9 is typically used to connect power grounds and I/O pads, and the most important M9 function is to evenly distribute power to each logic gate in the core. As a result, the importance of the peripheral area of ​​M9 is not as high as that of the central area, so that the signal network can share the peripheral area of ​​M9 with the network of the power supply.
Figure 5: First and second rewiring layers on the 9th and 10th layers, respectively. The power ground is placed in M_inner^L9. The area that can be routed is M_outer^L10 ∪ M_inner^L10 ∪ M_outer^L9.
The problem of rewiring layer wiring is manifested in the network Ni connecting the bump pad Bi and the input/output pad Oi. The first and second rewiring layers are M9 and M10, respectively, see Figure 5. We named this area as an internal/external area based on the boundary line. The entire rewiring layer is divided into four zones: M_inner^L9, M_outer^L9, M_inner^L10, and M_outer^L10.
Definition of Terms
◠Wiring area (pseudo-single layer): M_outer^L10 ∪ M_inner^L10 ∪ M_outer^L9
◠External area: M_outer^L10 ∪ M_outer^L9
◠Internal area: M_inner^L9 ∪ M_inner^L10
The wiring problem of the pseudo single-layer rewiring layer is to complete the actual connection of Bi and Oi of the network Ni in the routable area, and to minimize the area of ​​the inner area. This also means that the boundary line is not fixed. The solution is to determine the position of the boundary line.
Our pseudo single layer routing algorithm has four steps: the first step is regional layer allocation, removable pin assignment, and layout extraction. The second step is to complete the network cabling from a bump pad to a pin. The third step is to determine which line to use. The fourth step is to complete the routing from the I/O pad to the pin. Figure 6 shows a simple example of completing the moveable pin assignment process. The first step is the most important. A good removable pin assignment minimizes rewiring layer routing.
Figure 6: This simple example explains the routing process: (a) regional layer allocation, allocation of moveable pins, and layout extraction. Steps (b) and (d) describe which wire is used and how to route from the I/O pad to the pin using the channel wiring. (e) shows the wiring results of remapping into the original layout.
Figure 7: Two versions of the removable pin assignment: (a) A moveable pin assignment from a single-sided sort. (b) Removable pin assignment using the bump pin selection algorithm. The bump pin selection algorithm allows for routing results with fewer traces.
Figure 7 shows two methods of assigning removable pins. The first version completes the moveable pin assignment for each row of bumps from the same side, so the pin order and bump order are the same. This method can quickly complete the moveable pin assignment, but the disadvantage is that the order is fixed by the bump row. If the order of the bumps is not ideal, a large number of traces will be generated.
The second and recommended method is the pin selection algorithm, as shown in Figure 8. The first step produces all possible movable pin sequences and completes the bump-to-pin routing without any crossover network. The second step is to select the movable pin order from the first step on the principle of the minimum number of crossings. The bump selection algorithm ensures that there is no crossover of the bump-to-pin connections and the minimum number of pin-to-pad crossings. After using the bump selection algorithm, the channel routing algorithm completes the routing from the pin to the I/O pad, and determines the number of traces and allocates trace resources. Finally, the routing results are remapped to the original layout to complete the pseudo-single layer rewiring layer routing.
Figure 8: Bump selection algorithm. (a) Produce a movable pin sequence. (b) Select the pin order that minimizes the cross-connection between the movable pin and the I/O pad.
Verification validity
The above framework structure has been implemented in a large-scale commercial project. First, the chip is divided into four areas: W, N, E, and S. Each zone contains more than 100 signal bumps. For each zone, our router can produce results and complete the download of command scripts in less than 5 seconds. Physical routing is done by submitting these scripts in the Encounter Digital Implementation (EDI). This result can also be implemented with any pin-to-pin router because all pin locations are assigned. Design Rule Check (DRC) judges that all results are good. The wiring results are shown in Figures 6 and 7, and are summarized in Table I, where fcroute is the flip chip router in the defined EDI and p2proute is the point-to-point router. As there was no signing of the disclosure agreement, only partial results were shown.
Table I: Summary of wiring results.
Summary of this article
This article describes a method for completing rewiring layer routing on a pseudo-single layer that can be used in situations where too much congestion is not achieved by manual routing. The pseudo single layer routing approach provides a viable alternative to adding additional metal layers or increasing die size. The key to success is regional layer assignment, moveable pin assignment, and layout extraction. These techniques turn the wiring problem of the rewiring layer into a typical channel routing problem. With this method, 100% throughput can be achieved and the area of ​​the two-layer wiring can be minimized.
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