The Spartan-6 FPGA family offers low-risk and low-cost serial connectivity solutions for consumer, automotive, wireless and other price-sensitive or high-volume markets. The integrated endpoint module also has many handy features that simplify the design process and optimize the configuration of PCIe endpoint applications, with additional resources to provide a complete PCIe solution.
PCI Express 1.1 endpoint design with low risk, compatibility, and ease of configuration.
Provides PCIe endpoint and root port functionality with the GTP transceiver.
Built-in hard IP frees up user logic resources and reduces power consumption.
Passed the Gen1 compatibility verification of the PCI SIG.
Low-cost PCI technology supports compliance with 32-bit, 66MHz specifications.
Spartan-6 LXT FPGA device support.
Figure 2-53 shows the PCI-e hard IP block diagram in Spartan-6. This IP includes the transport layer, data link layer, physical layer, and configuration module. In addition, an internal logic access port is provided, and the serial interface with the outside world is implemented by GTP.
Figure 2-53 Spartan-6 PCI-e block diagram
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