Power Design Tip 27: Implement a buck IC for a simple and economical bias power supply circuit design (see PDF for the full text!)

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In this Power Design Tip, we'll look at a simple circuit that converts high AC input voltages into low DC voltages for applications such as electronic energy meters. In this particular application, there is no need to isolate the output voltage from the input voltage. Here, the rectified AC input voltage can be as high as 375 VDC, while the output voltage can be within 5 volts at hundreds of milliamps. These high-volume applications are often driven by cost, thus requiring low component count/low cost circuitry. Step-down regulators offer a low-cost solution, but they are challenging to implement with high-voltage inputs. In continuous mode, the duty cycle of the buck regulator is the output voltage divided by the input voltage, which is 1.25% when the 400V is converted to 5V. If we run the power supply at 100 kHz, an on-time of 125 nS is required, which is often impractical due to the switching rate limit.

The constant conduction controller (U1) drives a high voltage buck power stage that includes a P-channel FET (Q4) driven by a level shifting circuit (Q2, Q3) to convert 400V to 5V. This controller (using TPS64203 in our example) is the key to this design. It has a low quiescent current of 35 uA), allowing the converter to be started offline with minimal R2 and R3 resistor power dissipation. The second key factor is its ability to provide a short-time (600 nS) turn-on gate drive pulse to boost the minimum switching frequency (in continuous conduction mode) above 20 kHz. Q1 is used to level shift the gate drive voltage to the high side driver. The low voltage output from the IC is approximately 5 volts on R4, which causes a fixed current in Q1 and R5. Voltage is supplied to R5 through the emitter output to the P-channel FET gate. The current also charges C4 to power the drive circuit. We chose a P-channel FET to simplify the drive circuit. If an N-channel is to be used, a method that can drive the FET gate above the input voltage to completely enhance the device is required.

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