Multi-channel grating signal acquisition scheme based on FPGA

0 Preface

Grating sensors have been widely used as effective tools for precision mechanical measurement in online displacement, angular displacement, velocity, acceleration and other engineering measurements. In the length measurement, the grating micro-displacement sensor can achieve the measurement accuracy of μm level, and can dynamically acquire the change of the length, so that the motion speed and even the acceleration can be accurately calculated. In the surface measurement, compared with the traditional three-axis machine and profiler, the grating sensor also has the advantages of dynamic detection of surface shape change, high precision, and real-time output of face shape data.

The data acquisition of multi-path selection technology has been widely used. In some distributed systems, the use of multiple selection techniques can reduce the number of I/O ports and improve system integration. Specifically, the multi-channel selection switch is used to strobe the multi-channel signal, and the output end of the multi-way selection switch is connected to the I/O port of the acquisition chip, so that the acquisition chip samples the signals of each channel, but the sampling is repeated. The acquisition of the original waveform is discretized, that is, the waveform acquired needs to be processed before the chip processes the discrete signals acquired.

1 system overall plan

The system selected 60 high-precision grating sensors (with an accuracy of 0.5 μm) and arranged in a strip shape to measure the dynamic shape change of the circle.

In the actual measurement, 60 grating micro-displacement sensors are placed on the measuring table, and the shape to be tested is in contact with each sensor. When the shape of the surface to be measured changes, each grating sensor will generate corresponding displacement, and the surface will be at each collection point. The data changes are collected and the dynamic changes of the shape are restored by a certain interpolation algorithm.

Usually, the acquisition system uses FPGA as the acquisition chip of the grating signal. Because the number of signal channels involved in the system is large, it is difficult for a single-chip low-end FPGA to meet the requirements of signal acquisition. Therefore, multiple FPGAs need to work in parallel. Finally, a DSP chip or a single-chip microcomputer is used to address the values ​​of multiple FPGAs. Transfer the data of each sensor to the host computer, as shown in Figure 1. The system structure design is more complicated and the cost is higher.

Multi-chip parallel sampling schematic

This paper proposes a multi-channel signal acquisition scheme based on multi-path selection technology. For the problem that multiple signals cannot be collected by single chip at the same time, the method of string and combined sampling can be used to achieve the sampling accuracy requirements. Multi-channel signal acquisition on the FPGA, as shown in Figure 2.

Single chip serial and sampling diagram

In each sensor output signal, there are two signals (A, B) indicating the distance the sensor moves. The four sensors are grouped into one group and have eight signals (1A, ..., 4A, 1B, ..., 4B). 1A~4A is connected to 1Y0~1Y3 and 1B~4B of double 4-bit multi-way selector switch (such as 74HC4052). 2Y0~2Y3. FPGA of multi-way selection switch sends 2-bit control signal and controls the multi-select chip MUX1. When the control signal is 00, the 1Z output of MUX1 is 1A, and the output of 2Z is ​​1B. At this time, the signal received by the FPGA is the signal of sensor 1. When the control signal of the FPGA enters the next state 01, the 1Z output of MUX1 is 2A, and the output of 2Z is ​​2B. At this time, the signal of sensor 2 is acquired. By analogy, the signal from sensor 4 is then returned to sensor 1 again. This forms a process of cyclic sampling.

When the sampling frequency is not high, multi-channel parallel sampling can save a lot of IO resources, and the accuracy can be guaranteed. The state machine inside the FPGA can complete the control of multiple selection, as shown in Figure 3.

FPGA internal state machine

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