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Abstract: The SAA7144HL is a combination of four separate multi-standard video decoders, a full 3.3V CMOS circuit and a highly integrated video monitoring application circuit. The internal functions of the SAA7144HL are described in detail, and the typical application circuit of the SAA7144HL is given.Keywords: video input processor; SAA7144HL; composite TV broadcast signal
Introduction The SAA7144HL is a combination of four separate multi-standard video decoders, a full 3.3V CMOS circuit and a highly integrated video monitoring application circuit. Four video decoders based on the principle of line-locked clock decoding can decode color PAL, SECAM and NTSC signals into CCIR 601 compatible color component values, and can receive analog input from a total of 8 composite TV broadcast sources from TV or VTR. . The SAA7144HL's integrated high performance multi-standard data bidirectional limiter supports multiple VBI data standards.
2 Composition of SAA7144HL
   The functional block of the SAA7144HL is shown in Figure 1. Any of the four video decoders (A, B, C, D) includes a source selection analog processing circuit, an anti-aliasing filter, and an analog to digital converter for a two-way composite television broadcast signal (CVBS) source ( ADC), auto-clamp and SECAM and NTSC), brightness contrast saturation control circuit, multi-standard bidirectional limiter and a 27 MHz VBI data bypass.
The four decoders of the SAA7144HL are controlled by the I2C bus. The two decoders share a bus interface. The read feedback performance is controlled externally and the bit rate can reach 400 kbit/s. All standards shared by all decoders require only one 24.576 MHz quartz crystal. The decoder automatically detects field frequencies of 50 Hz and 60 Hz and automatically switches between PAL and NTSC standards. The 3.3V CMOS device has 5 V digital inputs and I/O ports. The SAA7144HL is available in a small LQFPl28 package.
3 Typical application design of SAA7144HL
3.1 Analog Control Circuit The anti-aliasing interference filter is adapted to the line lock clock frequency by the filter control circuit. Its characteristic curve is shown in Figure 2. There is no gain and clamp control function in the vertical blanking phase.
3.2 Clamp Circuit The clamp circuit controls the correct clamping of the analog input signal. The coupling capacitor is also used to store and filter the clamp voltage. An internal digital clamp comparator is used to generate information associated with the upper or lower clamp. The clamp stage of the dual ADC channel is determined by luminance (120) and chrominance (256). The commonly used clamp time is set by the trailing edge of the video HCL pulse.
3.3 Gain Control Circuit The gain control circuit receives the static gain stage of the analog amplifier through the I2C bus or automatically controls the amplifier through an AGC that is part of the analog input control (AICO).
Brightness automatic gain control amplifies the CVBS signal to the desired signal amplitude, matching the ADC input voltage range. The effective time of the AGC is synchronized with the bottom of the video signal.
3.4 The CGC inside the clock generation circuit generates all the clock signals required by the video input processor. The internal signal LFCO is a digital-to-analog conversion signal provided by a horizontal phase-locked loop (PLL), which is a multiple of the line frequency:
6.75 MHz = 429xfH (50 Hz), or 6.75 MHz = 432xfH (60 Hz)
The LFCO signal is multiplied by the 2 and 4 multiplication factors of the internal phase-locked loop circuit to obtain an output clock signal. The PLL circuit includes a phase detector, a loop filter, a voltage controlled oscillator (VCO), and a frequency divider. The rectangular output clock has a 50% duty cycle. The clock frequency is shown in Table 1, and the clock generation circuit block diagram is shown in Figure 3.
3.5 Multi-standard VBI bidirectional limiting circuit Multi-standard data bidirectional limiter is a VBI (Vertical Blanking Interval) and FF (Full Field) video data acquisition module. In combination with software modules, the limiter can capture broadcast VBI and FF data in almost all existing formats.
The implementation and programming model that matches the VBI data slicer is embedded in the multimedia video data acquisition circuit SAA5384. The circuit recovers the current clock phase during the clock run cycle, limits the number of data bits to the selected data rate, and groups them into bytes. The clock frequency, source, field frequency, and allowable error count must be specified by subaddress 40H, I2C bus of bits 7~4. Each VBI line can select multiple standards. The ideal standard for design is through the 41H~57H subaddress of the I2C bus (LCR2[7:0] to LCR24[7:0]). In order to adjust the limiter's processing of the signal source, the horizontal and vertical directions are completed by 5BH (bits 2~0), 59H (HOFF10~HOFF0) and 5BH (bit 4), 5AH (VOFF8~VOFFO) subaddresses of the I2C bus. Offset compensation.
The formatting operation of the VBI data decoding is done in the VPO bus output interface.
3.6 Unprocessed VBI Data Bypass For a 27 MHz unprocessed VBI data bypass, the digitized CVBS signal is upsampled after analog to digital conversion. The upsampled CVBS frequency component is obtained by an interpolation filter.
A typical application design block diagram of the SAA7144HL is shown in Figure 4.
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