Dma controller chip 8257 data introduction

DMA can refer to both computer technology that directly accesses memory and memory access to memory. It can also refer to the hardware module that implements this technology. For general-purpose computer PCs, DMA control logic is composed of CPU and DMA control interface logic chip. The DMA controller of the embedded system is built in the processor chip, generally called DMA controller, DMAC).

It's worth noting that only peripherals with large data traffic (kBps or higher) need to support DMA capabilities. Typical examples of these applications include video, audio, and network interfaces.

In the modern computer system, the structural mode in which the DMA controller is separated from the DMA interface is widely used as an example of the floppy disk drive DMA interface of the IBM-PC series microcomputer.

8237 DMA controller programming structure

Internal structure of the Intel 8237DMA controller chip

As shown below

Dma controller chip 8257 data introduction

The Intel 8257 is a chip that controls DMA (Direct Memory Access) operations. It can exchange data directly between the IO device and the memory without going through the CPU, so its data transfer rate can be fast.

The 8257 has the following features:

The 8257 has four channels, so it supports four devices for simultaneous DMA operations.

Each channel can be programmed independently and can transfer up to 64 kb of data at a time.

Each channel can independently perform read transfer, write transfer, and verify transfer.

The chip has a total of 40 pins, as shown below:

Dma controller chip 8257 data introduction

The 8257 function module is shown below:

- The 8257 function module has a data bus buffer, read/write logic, control logic, priority resolver and 4 DMA channels.

- Each DMA channel has two 16-bit programmable registers, an address register and a count register.

Dma controller chip 8257 data introduction

MEMR is the memory read operation signal, MEMW is the memory write operation signal, IOR is the peripheral read operation signal, and IOW is the peripheral write operation signal.

- The address register is used to store the memory start address for DMA data transfer.

- The address in the address register is automatically incremented after each read/write/verify transfer.

- The count register is used to count the number of bytes or words of data transferred by DMA. It keeps the number of bytes to transfer, and this register is decremented after each transfer. When the value of this register is reduced to zero, the Terminal Count signal will be generated.

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